[all-commits] [llvm/llvm-project] c32c0e: [RISCV] Add i32 as a legal type for GPR register c...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c32c0e14d6944d6a0e36191d7b5bf6943f96092e
      https://github.com/llvm/llvm-project/commit/c32c0e14d6944d6a0e36191d7b5bf6943f96092e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-26 (Mon, 26 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Add i32 as a legal type for GPR register class.

I'm investigating if it is feasible to have i32 as a legal type for RV64.
The first thing we need to do is make i32 a valid type for the GPR
register class.

We already added f32/f64 as valid types which required adding explicit
types to tablegen patterns. Adding additional types to GPR is free now.

Reviewed By: sunshaoce

Differential Revision: https://reviews.llvm.org/D151177