[all-commits] [llvm/llvm-project] 4c37d3: [RISCV] Add support for custom instructions for Si...

[garvit gupta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c37d30e22ae655394c8b3a7e292c06d393b9b44
      https://github.com/llvm/llvm-project/commit/4c37d30e22ae655394c8b3a7e292c06d393b9b44
  Author: Garvit Gupta <quic_garvgupt at quicinc.com>
  Date:   2023-06-26 (Mon, 26 Jun 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/xsfcie-invalid.s
    A llvm/test/MC/RISCV/xsfcie-valid.s

  Log Message:
  -----------
  [RISCV] Add support for custom instructions for Sifive S76.

Support for below instruction is added
1. CFLUSH.D.L1
2. CDISCARD.D.L1
3. CEASE

Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.

Spec - https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153370