Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: a1540e4852a90e7f72c996a3832edfd20968bd9e
https://github.com/llvm/llvm-project/commit/a1540e4852a90e7f72c996a3832edfd20968bd9e
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M clang/lib/CodeGen/MicrosoftCXXABI.cpp
M clang/test/CodeGenCXX/homogeneous-aggregates.cpp
Log Message:
-----------
[clang codegen] Fix ABI for HVA returns on AArch64 MSVC.
MSVC normally has a bunch of restrictions on returning values directly
which don't apply to passing values directly. (This roughly corresponds
to the definition of a C++14 aggregate.) However, these restrictions
don't apply to HVAs; make sure we check for that.
Fixes https://github.com/llvm/llvm-project/issues/62223
Differential Revision: https://reviews.llvm.org/D153179
Commit: bc7f11ccb01cbc2ae6c1631535ea5c181f70cb1e
https://github.com/llvm/llvm-project/commit/bc7f11ccb01cbc2ae6c1631535ea5c181f70cb1e
Author: Eli Friedman <efriedma at quicinc.com>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
M llvm/test/CodeGen/AArch64/fpclamptosat.ll
M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll
M llvm/test/CodeGen/AMDGPU/max.ll
M llvm/test/CodeGen/AMDGPU/min.ll
M llvm/test/CodeGen/ARM/fpclamptosat.ll
M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/fpclamptosat.ll
M llvm/test/CodeGen/RISCV/min-max.ll
M llvm/test/CodeGen/RISCV/rv32zbb.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
M llvm/test/CodeGen/Thumb2/mve-minmaxi.ll
M llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll
M llvm/test/CodeGen/VE/Scalar/smax.ll
M llvm/test/CodeGen/VE/Scalar/smin.ll
M llvm/test/CodeGen/VE/Scalar/umax.ll
M llvm/test/CodeGen/VE/Scalar/umin.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
M llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/abds.ll
M llvm/test/CodeGen/X86/abdu.ll
M llvm/test/CodeGen/X86/fpclamptosat.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/sdiv_fix_sat.ll
M llvm/test/CodeGen/X86/smax.ll
M llvm/test/CodeGen/X86/smin.ll
M llvm/test/CodeGen/X86/udiv_fix_sat.ll
M llvm/test/CodeGen/X86/umax.ll
M llvm/test/CodeGen/X86/umin.ll
Log Message:
-----------
[SelectionDAG] Improve expansion of wide min/max
The current implementation tries to handle the high and low halves
separately, but that's less efficient in most cases; use a wide SETCC
instead.
Differential Revision: https://reviews.llvm.org/D151358
Commit: 249bd9eab0aa122453073278bb9cd53f73c08cf8
https://github.com/llvm/llvm-project/commit/249bd9eab0aa122453073278bb9cd53f73c08cf8
Author: Maurice Heumann <MauriceHeumann at gmail.com>
Date: 2023-06-26 (Mon, 26 Jun 2023)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMSubtarget.h
M llvm/test/CodeGen/ARM/i64_volatile_load_store.ll
Log Message:
-----------
[ARM] Fix codegen of unaligned volatile load/store of i64
Volatile loads/stores of i64 are lowered to LDRD/STRD on ARMv5TE.
However, these instructions require the addresses to be aligned.
Unaligned loads/stores therefore should be ignored by this handling.
Differential Revision: https://reviews.llvm.org/D152790
Compare: https://github.com/llvm/llvm-project/compare/73eecc9ca4db...249bd9eab0aa