[all-commits] [llvm/llvm-project] 675694: [X86] lowerV8I16Shuffle - use PACKSS(SEXT_INREG(X)...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6756947ac6ef35f774817995c3e052ad48c83144
      https://github.com/llvm/llvm-project/commit/6756947ac6ef35f774817995c3e052ad48c83144
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-06-26 (Mon, 26 Jun 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/haddsub-shuf.ll
    M llvm/test/CodeGen/X86/vec_fp_to_int.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
    M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
    M llvm/test/CodeGen/X86/vector-trunc.ll

  Log Message:
  -----------
  [X86] lowerV8I16Shuffle - use PACKSS(SEXT_INREG(X),SEXT_INREG(Y)) for pre-SSSE3 truncation shuffles

The comment about PSHUFLW+PSHUFHW+PSHUFD was outdated as that referred to a single input case, but that is now always handled earlier.

Another step towards removing premature combines to vector truncation combines to PACK.


  Commit: 868351f894c3e4b36254efc3b09f20d1d479a8e3
      https://github.com/llvm/llvm-project/commit/868351f894c3e4b36254efc3b09f20d1d479a8e3
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-06-26 (Mon, 26 Jun 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    A llvm/test/CodeGen/X86/pr63507.ll

  Log Message:
  -----------
  [X86] combineMul - ensure getTargetConstantFromNode splat extraction is the correct element width

The extracted Constant and Constant::getSplatValue can both be any bitwidth - they don't necessarily match the original ConstantSDNode type

Fixes #63507


Compare: https://github.com/llvm/llvm-project/compare/a5d094c98f69...868351f894c3