[all-commits] [llvm/llvm-project] 43e57b: [RISCV] Add test case for D153490. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 43e57bda4ce1ef8cbef67a0b60cb822134c1f992
      https://github.com/llvm/llvm-project/commit/43e57bda4ce1ef8cbef67a0b60cb822134c1f992
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-25 (Sun, 25 Jun 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

  Log Message:
  -----------
  [RISCV] Add test case for D153490. NFC


  Commit: b105b3266fa06eb2f978fe2d22c2127236fbebbb
      https://github.com/llvm/llvm-project/commit/b105b3266fa06eb2f978fe2d22c2127236fbebbb
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-25 (Sun, 25 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

  Log Message:
  -----------
  [RISCV] Properly handle partial writes in isConvertibleToVMV_V_V.

We were only checking for the previous insructions to write exactly
the register or a super register. We ignored writes to a subregister
and continued searching for the producing instruction. We need to
abort instead.

There's another check inside the if body to abort if the registers
don't match exactly. So we just need to check for overlap so we
enter the if body.

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D153490


Compare: https://github.com/llvm/llvm-project/compare/f67dfb3cdb4b...b105b3266fa0