[all-commits] [llvm/llvm-project] 3f7772: [TargetLowering] Better code generation for ISD::S...

[Dhruv Chawla via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f77724de7bc84f5f6a89b81de990b2c49f93953
      https://github.com/llvm/llvm-project/commit/3f77724de7bc84f5f6a89b81de990b2c49f93953
  Author: Dhruv Chawla <44582521+dc03 at users.noreply.github.com>
  Date:   2023-06-23 (Fri, 23 Jun 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AArch64/aarch64-saturating-arithmetic.ll
    M llvm/test/CodeGen/X86/combine-add-ssat.ll

  Log Message:
  -----------
  [TargetLowering] Better code generation for ISD::SADDSAT/SSUBSAT when operand sign is known

When the sign of either of the operands is known, it is possible to
determine what the saturating value will be without having to compute it
using the sign bits.

Differential Revision: https://reviews.llvm.org/D153575