[all-commits] [llvm/llvm-project] 9d1bcb: [RISCV] Use GPR register class for RV64 ZDInx. Rem...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9d1bcb70ec8830ad85c0756a03022d3811537284
      https://github.com/llvm/llvm-project/commit/9d1bcb70ec8830ad85c0756a03022d3811537284
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-22 (Thu, 22 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td

  Log Message:
  -----------
  [RISCV] Use GPR register class for RV64 ZDInx. Remove GPRF64 register class.

The GPRF64 has the same spill size as GPR and is only used for RV64.
There's no real reason to have it as a separate class other than
for type inference for isel patterns in tablegen.

This patch adds f64 to the GPR register class when XLen=64. I use
f32 when XLen=32 even though we don't make use of it just to avoid
the oddity.

isel patterns have been updated to fix the lack of type infererence.

I might do similar for GPRF16 and GPRF32 or I might change them to
use an optimized spill size instead of always using XLen.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D153110