[all-commits] [llvm/llvm-project] 88f07a: [mlir][llvm] Fix import of SwitchOp

[Tobias Gysi via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 88f07a311947f88de82ad2de9b2d6a26eba21343
      https://github.com/llvm/llvm-project/commit/88f07a311947f88de82ad2de9b2d6a26eba21343
  Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
  Date:   2023-06-22 (Thu, 22 Jun 2023)

  Changed paths:
    M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
    M mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
    M mlir/lib/Target/LLVMIR/ModuleImport.cpp
    M mlir/test/Dialect/LLVMIR/invalid.mlir
    M mlir/test/Target/LLVMIR/Import/control-flow.ll

  Log Message:
  -----------
  [mlir][llvm] Fix import of SwitchOp

This revision ensures SwitchOps with case and condition
bitwidths other than 32-bit are imported properly. It adds an
APInt based builder to the SwitchOp and implements
a verifier that checks that the condition and the case
value types match.

Reviewed By: Dinistro

Differential Revision: https://reviews.llvm.org/D153438