[all-commits] [llvm/llvm-project] ddf3f1: [RISCV] Stop isInterleaveShuffle from producing il...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ddf3f1b3b21c94a212a0d2e97a47c80cee833854
      https://github.com/llvm/llvm-project/commit/ddf3f1b3b21c94a212a0d2e97a47c80cee833854
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

  Log Message:
  -----------
  [RISCV] Stop isInterleaveShuffle from producing illegal extract_subvectors.

The definition for ISD::EXTRACT_SUBVECTOR says the index must be
aligned to the known minimum elements of the extracted type. We mostly
got away with this but it turns out there are places that depend on this.

For example, this code in getNode for ISD::EXTRACT_SUBVECTOR

```
    // EXTRACT_SUBVECTOR of CONCAT_VECTOR can be simplified if the pieces of
    // the concat have the same type as the extract.
    if (N1.getOpcode() == ISD::CONCAT_VECTORS && N1.getNumOperands() > 0 &&
        VT == N1.getOperand(0).getValueType()) {
      unsigned Factor = VT.getVectorMinNumElements();
      return N1.getOperand(N2C->getZExtValue() / Factor);
    }
```

This depends on N2C->getZExtValue() being evenly divisible by Factor.

Reviewed By: luke

Differential Revision: https://reviews.llvm.org/D153380