[all-commits] [llvm/llvm-project] e219dd: [RISCV] Add support for XCVmac extension in CV32E40P

[realqhc via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e219dd88d1b61153805742587a9ed7f96b9faecc
      https://github.com/llvm/llvm-project/commit/e219dd88d1b61153805742587a9ed7f96b9faecc
  Author: Qihan Cai <qcai8733 at uni.sydney.edu.au>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    A llvm/test/MC/RISCV/corev/XCVmac-invalid.s
    A llvm/test/MC/RISCV/corev/XCVmac-valid.s

  Log Message:
  -----------
  [RISCV] Add support for XCVmac extension in CV32E40P

Implement XCVmac intrinsics for CV32E40P according to the specification.

This is the first commit of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

The patch-set aims at upstreaming the extensions on MC. The following will be on CodeGen, and the final patch-set will be on builtins if possible. The implemented version is on [0].

Contributors: @CharKeaney, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Spec: https://github.com/openhwgroup/cv32e40p/blob/62bec66b36182215e18c9cf10f723567e23878e9/docs/source/instruction_set_extensions.rst

[0] https://github.com/openhwgroup/corev-llvm-project

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152821