[all-commits] [llvm/llvm-project] c42f0a: PowerPC/SPE: Add phony registers for high halves ...

[Kishan Parmar via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c42f0a6e6476971974cb3f52c1138dbd8f9cca1f
      https://github.com/llvm/llvm-project/commit/c42f0a6e6476971974cb3f52c1138dbd8f9cca1f
  Author: Kishan Parmar <kparmar2101 at gmail.com>
  Date:   2023-06-21 (Wed, 21 Jun 2023)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
    M llvm/lib/Target/PowerPC/PPCRegisterInfo.td
    M llvm/test/CodeGen/PowerPC/fma-assoc.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-conv-spe.ll
    M llvm/test/CodeGen/PowerPC/fp-strict.ll
    M llvm/test/CodeGen/PowerPC/inline-asm-physical-fpr-spe.ll
    M llvm/test/CodeGen/PowerPC/pr55463.ll
    M llvm/test/CodeGen/PowerPC/spe.ll

  Log Message:
  -----------
  PowerPC/SPE:  Add phony registers for high halves of SPE SuperRegs

The intent of this patch is to make upper halves of SPE SuperRegs(s0,..,s31)
as artificial regs, similar to how X86 has done it.
And emit store /reload instructions for the required halves.

PR : https://github.com/llvm/llvm-project/issues/57307

Reviewed By: jhibbits

Differential Revision: https://reviews.llvm.org/D152437