[all-commits] [llvm/llvm-project] fb60dd: [GlobalIsel][X86] selectDivRem - fix typo in 64-bi...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fb60dda1893eb9d0420de25b84fb023dc8424aeb
      https://github.com/llvm/llvm-project/commit/fb60dda1893eb9d0420de25b84fb023dc8424aeb
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2023-06-18 (Sun, 18 Jun 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86InstructionSelector.cpp
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir

  Log Message:
  -----------
  [GlobalIsel][X86] selectDivRem - fix typo in 64-bit AH handling code

This function was lifted from fast-isel, and still referred to the Instruction::SRem/URrem opcodes, instead of the G_SREM/G_UREM opcodes.

But it turns out these aren't necessary at all as only the G_SREM/G_UREM codepaths will use the AH register for DivRemResultReg anyhow.