[all-commits] [llvm/llvm-project] 82d330: [AArch64] Try to convert vector shift operation in...

[JinGu Kang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 82d330e0e04a55ee95dc93980761545a01543fde
      https://github.com/llvm/llvm-project/commit/82d330e0e04a55ee95dc93980761545a01543fde
  Author: Jingu Kang <jingu.kang at arm.com>
  Date:   2023-06-16 (Fri, 16 Jun 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll
    M llvm/test/CodeGen/AArch64/rax1.ll
    A llvm/test/CodeGen/AArch64/shl-to-add.ll
    M llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll

  Log Message:
  -----------
  [AArch64] Try to convert vector shift operation into vector add operation

The vector shift instructions tend to be worse than ADD/SUB on AArch64 cores
so this patch supports tablegen patterns for below simple transformation.

 x << 1 ==> x + x

Differential Revision: https://reviews.llvm.org/D153049