[all-commits] [llvm/llvm-project] f87302: [BOLT] Add minimal RISC-V 64-bit support

[Job Noorman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f873029386dd415cd9caa78f600a593d9570c9ae
      https://github.com/llvm/llvm-project/commit/f873029386dd415cd9caa78f600a593d9570c9ae
  Author: Job Noorman <jnoorman at igalia.com>
  Date:   2023-06-16 (Fri, 16 Jun 2023)

  Changed paths:
    M bolt/CMakeLists.txt
    M bolt/CODE_OWNERS.TXT
    M bolt/include/bolt/Core/BinaryContext.h
    M bolt/include/bolt/Core/MCPlusBuilder.h
    A bolt/include/bolt/Passes/FixRISCVCallsPass.h
    M bolt/include/bolt/Rewrite/RewriteInstance.h
    M bolt/lib/Core/BinaryContext.cpp
    M bolt/lib/Core/BinaryFunction.cpp
    M bolt/lib/Core/Relocation.cpp
    M bolt/lib/Passes/CMakeLists.txt
    A bolt/lib/Passes/FixRISCVCallsPass.cpp
    M bolt/lib/Rewrite/BinaryPassManager.cpp
    M bolt/lib/Rewrite/RewriteInstance.cpp
    A bolt/lib/Target/RISCV/CMakeLists.txt
    A bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp
    A bolt/test/RISCV/Inputs/plt-gnu-ld.yaml
    A bolt/test/RISCV/lit.local.cfg
    A bolt/test/RISCV/plt-gnu-ld.test
    A bolt/test/RISCV/reloc-abs.s
    A bolt/test/RISCV/reloc-branch.s
    A bolt/test/RISCV/reloc-call.s
    A bolt/test/RISCV/reloc-got.s
    A bolt/test/RISCV/reloc-jal.s
    A bolt/test/RISCV/reloc-pcrel.s
    A bolt/test/RISCV/reloc-rvc-branch.s
    A bolt/test/RISCV/reloc-rvc-jump.s

  Log Message:
  -----------
  [BOLT] Add minimal RISC-V 64-bit support

Just enough features are implemented to process a simple "hello world"
executable and produce something that still runs (including libc calls).
This was mainly a matter of implementing support for various
relocations. Currently, the following are handled:

- R_RISCV_JAL
- R_RISCV_CALL
- R_RISCV_CALL_PLT
- R_RISCV_BRANCH
- R_RISCV_RVC_BRANCH
- R_RISCV_RVC_JUMP
- R_RISCV_GOT_HI20
- R_RISCV_PCREL_HI20
- R_RISCV_PCREL_LO12_I
- R_RISCV_RELAX
- R_RISCV_NONE

Executables linked with linker relaxation will probably fail to be
processed. BOLT relocates .text to a high address while leaving .plt at
its original (low) address. This causes PC-relative PLT calls that were
relaxed to a JAL to not fit their offset in an I-immediate anymore. This
is something that will be addressed in a later patch.

Changes to the BOLT core are relatively minor. Two things were tricky to
implement and needed slightly larger changes. I'll explain those below.

The R_RISCV_CALL(_PLT) relocation is put on the first instruction of a
AUIPC/JALR pair, the second does not get any relocation (unlike other
PCREL pairs). This causes issues with the combinations of the way BOLT
processes binaries and the RISC-V MC-layer handles relocations:
- BOLT reassembles instructions one by one and since the JALR doesn't
  have a relocation, it simply gets copied without modification;
- Even though the MC-layer handles R_RISCV_CALL properly (adjusts both
  the AUIPC and the JALR), it assumes the immediates of both
  instructions are 0 (to be able to or-in a new value). This will most
  likely not be the case for the JALR that got copied over.

To handle this difficulty without resorting to RISC-V-specific hacks in
the BOLT core, a new binary pass was added that searches for
AUIPC/JALR pairs and zeroes-out the immediate of the JALR.

A second difficulty was supporting ABS symbols. As far as I can tell,
ABS symbols were not handled at all, causing __global_pointer$ to break.
RewriteInstance::analyzeRelocation was updated to handle these
generically.

Tests are provided for all supported relocations. Note that in order to
test the correct handling of PLT entries, an ELF file produced by GCC
had to be used. While I tried to strip the YAML representation, it's
still quite large. Any suggestions on how to improve this would be
appreciated.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D145687