[all-commits] [llvm/llvm-project] fc9b26: [RISCV][InsertVSETVLI] Treat vmv.v.i as-if it were...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fc9b26440d4441a0b3bcb9202debe259b57f4692
      https://github.com/llvm/llvm-project/commit/fc9b26440d4441a0b3bcb9202debe259b57f4692
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-06-15 (Thu, 15 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

  Log Message:
  -----------
  [RISCV][InsertVSETVLI] Treat vmv.v.i as-if it were vmv.s.x when VL=1, and inactive lanes are undefined

A vmv.v.i/x splats the immediate to all active lanes. For the active lanes, this is the same as vmv.s.x which inserts one scalar into the low lane. If we can ignore all the inactive lanes (because they are known undefined), then the two are semantically equivalent. We already reason about compatible VL/VTYPE combinations for vmv.s.x, apply the same logic to vmv.v.i.

Unlike a vmv.s.x, we do need to be careful not to increase LMUL. A splat instruction is probably linear in LMUL, so restrict this to LMUL1.

Differential Revision: https://reviews.llvm.org/D152845