[all-commits] [llvm/llvm-project] fcc9fa: [RISCV] Reduce the number of ExtInfo_rr permutatio...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fcc9fa55a76a009ececfb1656142d3d7b0842489
      https://github.com/llvm/llvm-project/commit/fcc9fa55a76a009ececfb1656142d3d7b0842489
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-14 (Wed, 14 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

  Log Message:
  -----------
  [RISCV] Reduce the number of ExtInfo_rr permutations in tablegen.

Add ExtraPreds parameter to FPUnaryOp_r_frm_m to pass IsRV64 so we
don't need RV64 versions of ExtInfo_rr.

Differential Revision: https://reviews.llvm.org/D152890