[all-commits] [llvm/llvm-project] a48fe8: [mlir][ArmSME] Add initial dialect with basic lowe...

Cullen Rhodes via All-commits all-commits at lists.llvm.org
Wed Jun 14 01:47:38 PDT 2023


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a48fe898857c95a063fa6c201343dca969bc098a
      https://github.com/llvm/llvm-project/commit/a48fe898857c95a063fa6c201343dca969bc098a
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2023-06-14 (Wed, 14 Jun 2023)

  Changed paths:
    M mlir/include/mlir/Conversion/Passes.td
    M mlir/include/mlir/Dialect/ArmSME/CMakeLists.txt
    A mlir/include/mlir/Dialect/ArmSME/IR/ArmSME.td
    A mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEDialect.h
    A mlir/include/mlir/Dialect/ArmSME/IR/CMakeLists.txt
    A mlir/include/mlir/Dialect/ArmSME/Transforms/Transforms.h
    M mlir/include/mlir/InitAllDialects.h
    M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
    A mlir/include/mlir/Target/LLVMIR/Dialect/ArmSME/ArmSMEToLLVMIRTranslation.h
    M mlir/lib/Conversion/VectorToLLVM/CMakeLists.txt
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
    M mlir/lib/Dialect/ArmSME/CMakeLists.txt
    A mlir/lib/Dialect/ArmSME/IR/ArmSMEDialect.cpp
    A mlir/lib/Dialect/ArmSME/IR/CMakeLists.txt
    M mlir/lib/Dialect/ArmSME/Transforms/CMakeLists.txt
    A mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
    A mlir/lib/Dialect/ArmSME/Transforms/LowerVectorOps.cpp
    M mlir/lib/Dialect/Vector/Transforms/CMakeLists.txt
    M mlir/lib/Target/LLVMIR/CMakeLists.txt
    A mlir/lib/Target/LLVMIR/Dialect/ArmSME/ArmSMEToLLVMIRTranslation.cpp
    A mlir/lib/Target/LLVMIR/Dialect/ArmSME/CMakeLists.txt
    M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
    A mlir/test/Dialect/ArmSME/vector_ops.mlir
    A mlir/test/Target/LLVMIR/arm-sme.mlir

  Log Message:
  -----------
  [mlir][ArmSME] Add initial dialect with basic lowering of vector.transfer write to zero

This patch adds support for lowering a `vector.transfer_write` of zeroes
and type `vector<[16x16]xi8>` to the SME `zero {za}` instruction [1],
which zeroes the entire accumulator.

This contributes to supporting a path from `linalg.fill` to SME.

[1] https://developer.arm.com/documentation/ddi0602/2022-06/SME-Instructions/ZERO--Zero-a-list-of-64-bit-element-ZA-tiles-

Reviewed By: awarzynski, dcaballe

Differential Revision: https://reviews.llvm.org/D152508




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