[all-commits] [llvm/llvm-project] 6ac2ce: [RISCV] Introduce the concept of DLEN(data path wi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6ac2ce7d844c30e818dc4ea100d96c165a465edc
      https://github.com/llvm/llvm-project/commit/6ac2ce7d844c30e818dc4ea100d96c165a465edc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-13 (Tue, 13 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.h
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
    M llvm/test/Analysis/CostModel/RISCV/arith-int.ll

  Log Message:
  -----------
  [RISCV] Introduce the concept of DLEN(data path width) into getLMULCost.

SiFive's x280 CPU has a vector unit that VLEN/2 bits wide. This
means that LMUL=1 operations take 2 to process all VLEN bits.

This patch adds a DLenFactor tuning parameter and applies it to
TuneSiFive7. getLMULCost has been updated to use this factor in
its calculations. I've added an x280 command line to one cost
model test to demonstrate the effect.

Reviewed By: arcbbb

Differential Revision: https://reviews.llvm.org/D152421