[all-commits] [llvm/llvm-project] 17e2d0: [RISCV] Use tail undisturbed vmv.v.v instead of vs...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 17e2d07ad15e02c9c757fdd4a532c43747ed8bf3
      https://github.com/llvm/llvm-project/commit/17e2d07ad15e02c9c757fdd4a532c43747ed8bf3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-12 (Mon, 12 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
    M llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

  Log Message:
  -----------
  [RISCV] Use tail undisturbed vmv.v.v instead of vslideup.vi vN, vM, 0 for subvector insertion

vslideup has a vector overlap constraint that vmv.v.v doesn't.
vmv.v.v is also a simpler instruction so may have better
throughput and/or latency in some CPUs.

This is an alternative to D152298, D152368, and D152496.

Reviewed By: luke, reames

Differential Revision: https://reviews.llvm.org/D152565