[all-commits] [llvm/llvm-project] 72d23a: [RISCV] Support LMUL!=1 for __attribute__((riscv_r...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 72d23a2ec1b98c26aa3a85b83118d969ae286928
      https://github.com/llvm/llvm-project/commit/72d23a2ec1b98c26aa3a85b83118d969ae286928
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-08 (Thu, 08 Jun 2023)

  Changed paths:
    M clang/include/clang/Basic/AttrDocs.td
    M clang/include/clang/Basic/DiagnosticSemaKinds.td
    M clang/lib/AST/ASTContext.cpp
    M clang/lib/AST/Type.cpp
    M clang/lib/Sema/SemaType.cpp
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
    M clang/test/CodeGen/attr-riscv-rvv-vector-bits-types.c
    M clang/test/Driver/riscv-rvv-vector-bits.c
    M clang/test/Sema/attr-riscv-rvv-vector-bits.c

  Log Message:
  -----------
  [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

The first patch supported only LMUL=1 types. This patch supports
LMUL!=1.

LMUL is length multiplier that allows multiple vector registers to
be treated as one large register or a fraction of a single vector
register. Supported values for LMUL are 1/8, 1/4, 1/2, 1, 2, 4, and 8.

An LMUL=2 type will be twice as large as an LMUL=1 type. An LMUL=1/2
type will be half the size as an LMUL=1 type.

Type name with "m2" is LMUL=2, "m4" is LMUL=4.
Type name with "mf2" is LMUL=1/2, "mf4" is LMUL=1/4.

For the LMUL!=1 types the user will need to scale __riscv_v_fixed_vlen
by the LMUL before passing to the attribute.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D150926