[all-commits] [llvm/llvm-project] 4f5f38: [RISCV] Add early out to generateInstSeq when the ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4f5f38bdabe55ecc8ba18b0a42207341e0bc5d96
      https://github.com/llvm/llvm-project/commit/4f5f38bdabe55ecc8ba18b0a42207341e0bc5d96
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-06 (Tue, 06 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

  Log Message:
  -----------
  [RISCV] Add early out to generateInstSeq when the initial sequence is 1 or 2 instructions.

This avoids checking the size of the sequence repeatedly for each
special case. Especially on RV32 where none of the special cases
apply.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D152300