[all-commits] [llvm/llvm-project] 77da27: [RISCV] Improve selection for vector fpclass.

[Jianjian Guan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 77da27b5e36ce74ad584da331b568d6d757343a8
      https://github.com/llvm/llvm-project/commit/77da27b5e36ce74ad584da331b568d6d757343a8
  Author: Jianjian GUAN <jacquesguan at me.com>
  Date:   2023-06-06 (Tue, 06 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfclass.ll
    M llvm/test/CodeGen/RISCV/rvv/vfclass-sdnode.ll

  Log Message:
  -----------
  [RISCV] Improve selection for vector fpclass.

Since vfclass intruction will only set one single bit in the result, so if we only want to check 1 fp class, we could use vmseq to do it.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D151967