[all-commits] [llvm/llvm-project] b64dda: [RISCV] Lower experimental_get_vector_length intri...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b64ddae8a294605819470ce2f8d8b4751d0ffe12
      https://github.com/llvm/llvm-project/commit/b64ddae8a294605819470ce2f8d8b4751d0ffe12
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-06-05 (Mon, 05 Jun 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll

  Log Message:
  -----------
  [RISCV] Lower experimental_get_vector_length intrinsic to vsetvli for some cases.

This patch lowers to vsetvli when the AVL is i32 or XLenVT and
the VF is a power of 2 in the range [1, 64]. VLEN=32 is not supported
as we don't have a valid type mapping for that. VF=1 is not supported
with Zve32* only.

The element width is used to set the SEW for the vsetvli if possible.
Otherwise we use SEW=8.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D150824