[all-commits] [llvm/llvm-project] dc90f4: Coalesce 16-bit FP types to use integer register c...

[Artem Belevich via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dc90f42ea7b4f6d9e643f5ad2ba663eba2f9e421
      https://github.com/llvm/llvm-project/commit/dc90f42ea7b4f6d9e643f5ad2ba663eba2f9e421
  Author: Artem Belevich <tra at google.com>
  Date:   2023-06-05 (Mon, 05 Jun 2023)

  Changed paths:
    M clang/test/CodeGenCUDA/bf16.cu
    M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
    M llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
    M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
    M llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp
    M llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
    M llvm/test/CodeGen/NVPTX/bf16.ll
    M llvm/test/CodeGen/NVPTX/call_bitcast_byval.ll
    M llvm/test/CodeGen/NVPTX/f16-instructions.ll
    M llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
    M llvm/test/CodeGen/NVPTX/half.ll
    M llvm/test/CodeGen/NVPTX/intrinsics-sm90.ll
    M llvm/test/CodeGen/NVPTX/ld-st-addrrspace.py
    M llvm/test/CodeGen/NVPTX/ldg-invariant.ll
    M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
    M llvm/test/CodeGen/NVPTX/param-load-store.ll
    M llvm/test/CodeGen/NVPTX/proxy-reg-erasure-ptx.ll
    M llvm/test/CodeGen/NVPTX/wmma.py

  Log Message:
  -----------
  Coalesce 16-bit FP types to use integer register classes.

i16/f16/bf16 will use the same .b16 registers and
i32/v2f16 and v2bf16 will share .b32 registers.

The changes are mostly mechanical, intended to remove unnecessary register
classes which tend to produce redundant register moves.

Differential Revision: https://reviews.llvm.org/D151601

v2f16 regtype conversion to i32