[all-commits] [llvm/llvm-project] faa2c6: [AMDGPU] Add buffer intrinsics that take resources...

Krzysztof Drewniak via All-commits all-commits at lists.llvm.org
Mon Jun 5 09:59:20 PDT 2023 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: faa2c678aa1963147af35c3700e6b44c264af99f
      https://github.com/llvm/llvm-project/commit/faa2c678aa1963147af35c3700e6b44c264af99f
  Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
  Date:   2023-06-05 (Mon, 05 Jun 2023)

  Changed paths:
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/llvm.amdgcn.buffer.atomic.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-schedule.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    R llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.buffer.ptr.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.ptr.buffer.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.format.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.store.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.format.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.store.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.raw.ptr.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.struct.ptr.buffer.store.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-load.ll
    A llvm/test/CodeGen/AMDGPU/GlobalISel/unsupported-ptr-add.ll
    M llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
    M llvm/test/CodeGen/AMDGPU/amdpal.ll
    M llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
    M llvm/test/CodeGen/AMDGPU/bitcast-v4f16-v4i16.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f32-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.f64.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-no-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-atomic-fadd.v2f16-rtn.ll
    M llvm/test/CodeGen/AMDGPU/buffer-intrinsics-mmo-offsets.ll
    A llvm/test/CodeGen/AMDGPU/buffer-rsrc-ptr-ops.ll
    M llvm/test/CodeGen/AMDGPU/buffer-schedule.ll
    M llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
    M llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
    M llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll
    M llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
    M llvm/test/CodeGen/AMDGPU/copy_to_scc.ll
    M llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll
    M llvm/test/CodeGen/AMDGPU/else.ll
    M llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
    M llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
    A llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    A llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll
    M llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll
    M llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.f16.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.format.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f16.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.format.f32.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.buffer.store.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.f16.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.load.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.f16.ll
    A llvm/test/CodeGen/AMDGPU/legalize-amdgcn.raw.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/legalize-soffset-mbuf.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
    R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.hsa.ll
    R llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.format.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.store.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.v3f16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.lds.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.format.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.store.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.d16.ll
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.store.ll
    M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
    M llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll
    M llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
    M llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll
    A llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
    A llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
    M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
    M llvm/test/CodeGen/AMDGPU/mubuf.ll
    M llvm/test/CodeGen/AMDGPU/set-inactive-wwm-overwrite.ll
    M llvm/test/CodeGen/AMDGPU/set-wave-priority.ll
    M llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll
    M llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll
    M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
    M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
    M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
    M llvm/test/CodeGen/AMDGPU/wait.ll
    M llvm/test/CodeGen/AMDGPU/wave32.ll
    M llvm/test/CodeGen/AMDGPU/wqm.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
    M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
    M llvm/test/CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll
    M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
    M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll
    A llvm/test/Transforms/LICM/AMDGPU/buffer-rsrc-ptrs.ll
    M llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
    M llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
    M llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop.ll

  Log Message:
  -----------
  [AMDGPU] Add buffer intrinsics that take resources as pointers

In order to enable the LLVM frontend to better analyze buffer
operations (and to potentially enable more precise analyses on the
backend), define versions of the raw and structured buffer intrinsics
that use `ptr addrspace(8)` instead of `<4 x i32>` to represent their
rsrc arguments.

The new intrinsics are named by replacing `buffer.` with `buffer.ptr`.

One advantage to these intrinsic definitions is that, instead of
specifying that a buffer load/store will read/write some memory, we
can indicate that the memory read or written will be based on the
pointer argument. This means that, for example, a read from a
`noalias` buffer can be pulled out of a loop that is modifying a
distinct buffer.

In the future, we will define custom PseudoSourceValues that will
allow us to package up the (buffer, index, offset) triples that buffer
intrinsics contain and allow for more precise backend analysis.

This work also enables creating address space 7, which represents
manipulation of raw buffers using native LLVM load and store
instructions.

Where tests simply used a buffer intrinsic while testing some other
code path (such as the tests for VGPR spills), they have been updated
to use the new intrinsic form. Tests that are "about" buffer
intrinsics (for instance, those that ensure that they codegen as
expected) have been duplicated, either within existing files or into
new ones.

Depends on D145441

Reviewed By: arsenm, #amdgpu

Differential Revision: https://reviews.llvm.org/D147547

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