[all-commits] [llvm/llvm-project] e69fa0: [DAGCombine] Make sure combined nodes are added ba...

Mon Jun 5 04:09:34 PDT 2023

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e69fa03ddd85812be3143d79a0359c3e8d43bd45
      https://github.com/llvm/llvm-project/commit/e69fa03ddd85812be3143d79a0359c3e8d43bd45
  Author: Amaury Séchet <deadalnix at gmail.com>
  Date:   2023-06-05 (Mon, 05 Jun 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/combine-cond-add-sub.ll
    M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
    M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
    M llvm/test/CodeGen/AMDGPU/ds_write2.ll
    M llvm/test/CodeGen/AMDGPU/idot4u.ll
    M llvm/test/CodeGen/AMDGPU/idot8s.ll
    M llvm/test/CodeGen/AMDGPU/idot8u.ll
    M llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll
    M llvm/test/CodeGen/AMDGPU/store-local.128.ll
    M llvm/test/CodeGen/AMDGPU/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll
    M llvm/test/CodeGen/ARM/addsubcarry-promotion.ll
    M llvm/test/CodeGen/ARM/icmp-shift-opt.ll
    M llvm/test/CodeGen/ARM/reg_sequence.ll
    M llvm/test/CodeGen/Hexagon/autohvx/isel-vpackew.ll
    M llvm/test/CodeGen/Hexagon/autohvx/mulh.ll
    M llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll
    M llvm/test/CodeGen/PowerPC/combine-fneg.ll
    M llvm/test/CodeGen/PowerPC/select_const.ll
    M llvm/test/CodeGen/RISCV/mul.ll
    M llvm/test/CodeGen/RISCV/pr58511.ll
    M llvm/test/CodeGen/SystemZ/pr36164.ll
    M llvm/test/CodeGen/Thumb2/mve-vst3.ll
    M llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
    M llvm/test/CodeGen/X86/2012-08-07-CmpISelBug.ll
    M llvm/test/CodeGen/X86/addcarry.ll
    M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
    M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
    M llvm/test/CodeGen/X86/avx512-mask-op.ll
    M llvm/test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll
    M llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
    M llvm/test/CodeGen/X86/bitcast-vector-bool.ll
    M llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
    M llvm/test/CodeGen/X86/dagcombine-select.ll
    M llvm/test/CodeGen/X86/field-extract-use-trunc.ll
    M llvm/test/CodeGen/X86/horizontal-sum.ll
    M llvm/test/CodeGen/X86/icmp-shift-opt.ll
    M llvm/test/CodeGen/X86/insertelement-var-index.ll
    M llvm/test/CodeGen/X86/is_fpclass-fp80.ll
    M llvm/test/CodeGen/X86/isel-blendi-gettargetconstant.ll
    M llvm/test/CodeGen/X86/masked_store.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
    M llvm/test/CodeGen/X86/movmsk-cmp.ll
    M llvm/test/CodeGen/X86/mulvi32.ll
    M llvm/test/CodeGen/X86/nontemporal-3.ll
    M llvm/test/CodeGen/X86/pmulh.ll
    M llvm/test/CodeGen/X86/popcnt.ll
    M llvm/test/CodeGen/X86/promote-vec3.ll
    M llvm/test/CodeGen/X86/psubus.ll
    M llvm/test/CodeGen/X86/shift-mask.ll
    M llvm/test/CodeGen/X86/shuffle-strided-with-offset-128.ll
    M llvm/test/CodeGen/X86/single_elt_vector_memory_operation.ll
    M llvm/test/CodeGen/X86/smax.ll
    M llvm/test/CodeGen/X86/smin.ll
    M llvm/test/CodeGen/X86/smulo-128-legalisation-lowering.ll
    M llvm/test/CodeGen/X86/umax.ll
    M llvm/test/CodeGen/X86/umin.ll
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-512.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-512.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-reduce-and-bool.ll
    M llvm/test/CodeGen/X86/vector-reduce-and.ll
    M llvm/test/CodeGen/X86/vector-reduce-or-bool.ll
    M llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
    M llvm/test/CodeGen/X86/vector-reduce-or.ll
    M llvm/test/CodeGen/X86/vector-reduce-xor.ll
    M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
    M llvm/test/CodeGen/X86/vector-rotate-256.ll
    M llvm/test/CodeGen/X86/vector-rotate-512.ll
    M llvm/test/CodeGen/X86/vector-shuffle-concatenation.ll
    M llvm/test/CodeGen/X86/vector-shuffle-sse4a.ll
    M llvm/test/CodeGen/X86/vector-zext.ll
    M llvm/test/CodeGen/X86/wide-integer-cmp.ll
    M llvm/test/CodeGen/X86/widen-load-of-small-alloca-with-zero-upper-half.ll
    M llvm/test/CodeGen/X86/xaluo128.ll
    M llvm/test/CodeGen/X86/xor.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll

  Log Message:
  -----------
  [DAGCombine] Make sure combined nodes are added back to the worklist in topological order.

Currently, a node and its users are added back to the worklist in reverse topological order after it is combined. This diff changes that order to be topological. This is part of a larger migration to get the DAGCombiner to process nodes in topological order.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D127115