[all-commits] [llvm/llvm-project] aa7eac: [TableGen][GlobalISel] Account for HwMode in Regis...

[Nitin John Raj via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aa7eace8431ba213c5431638b894b0e1b4b481c7
      https://github.com/llvm/llvm-project/commit/aa7eace8431ba213c5431638b894b0e1b4b481c7
  Author: Nitin John Raj <nitin.raj at sifive.com>
  Date:   2023-06-02 (Fri, 02 Jun 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/RegisterBank.h
    M llvm/include/llvm/CodeGen/RegisterBankInfo.h
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/RegisterBank.cpp
    M llvm/lib/CodeGen/RegisterBankInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/lib/Target/X86/X86RegisterBankInfo.cpp
    M llvm/utils/TableGen/RegisterBankEmitter.cpp

  Log Message:
  -----------
  [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

This patch adds logic for determining RegisterBank size to RegisterBankInfo, which allows accounting for the HwMode of the target. Individual RegisterBanks cannot be constructed with HwMode information as construction is generated by TableGen, but a RegisterBankInfo subclass can provide the HwMode as a constructor argument. The HwMode is used to select the appropriate RegisterBank size from an array relating sizes to RegisterBanks.

Targets simply need to provide the HwMode argument to the <target>GenRegisterBankInfo constructor. The RISC-V RegisterBankInfo constructor has been updated accordingly (plus an unused argument removed).

Reviewed By: simoncook, craig.topper

Differential Revision: https://reviews.llvm.org/D76007