[all-commits] [llvm/llvm-project] 463f50: [RISCV] Add RISCVISD::VFWMUL_VL. Use it to replace...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 463f50b436a2ac3000a90d273f2ed05893e8864f
      https://github.com/llvm/llvm-project/commit/463f50b436a2ac3000a90d273f2ed05893e8864f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-30 (Tue, 30 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Add RISCVISD::VFWMUL_VL. Use it to replace isel patterns with a DAG combine.

This is more consistent with how we handle integer widening multiply.

A follow up patch will add support for matching vfwmul when the
multiplicand is being squared.