[all-commits] [llvm/llvm-project] 28ab03: [RISCV] Add isel patterns to form tail undisturbed...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 28ab032298824ed1cd6d1499a7c67cffbf11faa3
      https://github.com/llvm/llvm-project/commit/28ab032298824ed1cd6d1499a7c67cffbf11faa3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-26 (Fri, 26 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    A llvm/test/CodeGen/RISCV/rvv/vfwadd-vp.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns to form tail undisturbed vfwadd.wv from fpextend_vl+vfwadd_vl+vp_merge.

We use a special TIED instructions for vfwadd.wv to avoid an
earlyclobber constraint preventing the first source and the destination
from being the same register.

This prevents our normal post process for forming TU instructions.
Add manual isel pattern instead. This matches what we do for FMA
for example.