[all-commits] [llvm/llvm-project] a4f437: SelectionDAG: Teach ComputeKnownBits about VSCALE

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a4f437f012b4be40e9fac5d2e86eae549d3469fe
      https://github.com/llvm/llvm-project/commit/a4f437f012b4be40e9fac5d2e86eae549d3469fe
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-26 (Fri, 26 May 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll
    A llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll

  Log Message:
  -----------
  SelectionDAG: Teach ComputeKnownBits about VSCALE

This reverts commit 9b92f70d4758f75903ce93feaba5098130820d40.  The issue
with the re-applied change was an implicit truncation due to the
multiplication.  Although the operations were converted to `APInt`, the
values were implicitly converted to `long` due to the typing rules.

Fixes: #59594

Differential Revision: https://reviews.llvm.org/D140347