[all-commits] [llvm/llvm-project] c5e6c8: [VP][SelectionDAG][RISCV] Add get_vector_length in...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c5e6c886aabb36ab66b4ed835da243c2a3455ade
      https://github.com/llvm/llvm-project/commit/c5e6c886aabb36ab66b4ed835da243c2a3455ade
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-26 (Fri, 26 May 2023)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/CodeGen/SelectionDAG.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/IR/Verifier.cpp
    A llvm/test/CodeGen/AArch64/get_vector_length.ll
    A llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
    A llvm/test/Verifier/get_vector_length.ll

  Log Message:
  -----------
  [VP][SelectionDAG][RISCV] Add get_vector_length intrinsics and generic SelectionDAG support.

The generic implementation is umin(TC, VF * vscale).

Lowering to vsetvli for RISC-V will come in a future patch.

This patch is a pre-requisite to be able to CodeGen vectorized code from
D99750.

Reviewed By: reames, frasercrmck

Differential Revision: https://reviews.llvm.org/D149916