[all-commits] [llvm/llvm-project] e4284a: [AMDGPU] 4-align SGPR triples

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e4284a7c70cd6af818922cbe9722940fa2134ec0
      https://github.com/llvm/llvm-project/commit/e4284a7c70cd6af818922cbe9722940fa2134ec0
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2023-05-26 (Fri, 26 May 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
    M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
    M llvm/test/CodeGen/AMDGPU/copy-overlap-sgpr-kill.mir
    M llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll
    M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
    M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll

  Log Message:
  -----------
  [AMDGPU] 4-align SGPR triples

Previously SGPR triples like s[3:5] were aligned on a 3-SGPR boundary
which has no basis in hardware.

Aligning them on a 4-SGPR boundary is at least justified by the
architecture reference guide which says: "Quad-alignment of SGPRs is
required for operation on more than 64-bits".

Currently there are no instructions that take SGPR triples as operands
so the issue is latent.

Differential Revision: https://reviews.llvm.org/D151463