[all-commits] [llvm/llvm-project] c4a60c: [CodeGen][ShrinkWrap] Enable PostShrinkWrap by def...

[sushgokh via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c4a60c9d34375e73fc2da5e02215eabe4bc90e8f
      https://github.com/llvm/llvm-project/commit/c4a60c9d34375e73fc2da5e02215eabe4bc90e8f
  Author: sgokhale <sgokhale at nvidia.com>
  Date:   2023-05-25 (Thu, 25 May 2023)

  Changed paths:
    M llvm/lib/CodeGen/ShrinkWrap.cpp
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
    M llvm/test/CodeGen/AArch64/ragreedy-csr.ll
    A llvm/test/CodeGen/AArch64/shrinkwrap-split-restore-point.mir
    M llvm/test/CodeGen/AArch64/taildup-cfi.ll
    M llvm/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
    M llvm/test/CodeGen/ARM/code-placement.ll
    M llvm/test/CodeGen/ARM/mbp.ll
    M llvm/test/CodeGen/ARM/ssat-unroll-loops.ll
    M llvm/test/CodeGen/PowerPC/common-chain-aix32.ll
    M llvm/test/CodeGen/PowerPC/common-chain.ll
    M llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
    M llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll
    M llvm/test/CodeGen/PowerPC/shrink-wrap.ll
    M llvm/test/CodeGen/PowerPC/shrink-wrap.mir
    M llvm/test/CodeGen/RISCV/aext-to-sext.ll
    M llvm/test/CodeGen/RISCV/fli-licm.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inlineasm.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/memcall.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/sibling-loops.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/spillingmove.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
    M llvm/test/CodeGen/Thumb2/mve-gather-tailpred.ll
    M llvm/test/CodeGen/Thumb2/mve-memtp-loop.ll
    M llvm/test/CodeGen/Thumb2/mve-postinc-dct.ll
    M llvm/test/CodeGen/Thumb2/mve-scatter-increment.ll
    M llvm/test/CodeGen/Thumb2/mve-tailpred-nonzerostart.ll
    M llvm/test/CodeGen/Thumb2/mve-vmull-loop.ll
    M llvm/test/CodeGen/X86/fold-call-3.ll
    M llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll
    M llvm/test/CodeGen/X86/pr44412.ll
    M llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
    M llvm/test/Transforms/LoopStrengthReduce/AArch64/pr53625.ll
    M llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll

  Log Message:
  -----------
  [CodeGen][ShrinkWrap] Enable PostShrinkWrap by default

This is an attempt to reland D42600 and enabling this optimisation by default.

This also resolves the issue pointed out in the context of PGO build.

Differential Revision: https://reviews.llvm.org/D42600