[all-commits] [llvm/llvm-project] 139392: [LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembl...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 139392c0a58008b7451e1a1943f5022dc920928b
      https://github.com/llvm/llvm-project/commit/139392c0a58008b7451e1a1943f5022dc920928b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-23 (Tue, 23 May 2023)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/test/CodeGen/AArch64/fpclamptosat.ll
    M llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
    M llvm/test/CodeGen/ARM/fpclamptosat.ll
    M llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/fpclamptosat.ll
    M llvm/test/CodeGen/RISCV/min-max.ll
    M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
    M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
    M llvm/test/CodeGen/VE/Scalar/smax.ll
    M llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
    M llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll

  Log Message:
  -----------
  [LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.

We can compute a simpler expression for Lo for these cases. This
is an alternative for the test cases in D151180 that works for
more targets.

This is similar to some of the special cases we have for expanding
setcc operands.

Differential Revision: https://reviews.llvm.org/D151182