[all-commits] [llvm/llvm-project] 5734a8: [RISCV] Increase scalar integer divide latency for...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5734a81a5527dec3e63bebe842ac0bb9e2ff9025
      https://github.com/llvm/llvm-project/commit/5734a81a5527dec3e63bebe842ac0bb9e2ff9025
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-22 (Mon, 22 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Increase scalar integer divide latency for SiFive7.

The scalar divider produces 1 bit per cycle so the worst case
latency is the input width plus a couple cycles.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D151139