[all-commits] [llvm/llvm-project] 490764: [RISCV] Fix some errors in the vector part of the ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 490764985395c611720c30a2684ddaab485001ea
      https://github.com/llvm/llvm-project/commit/490764985395c611720c30a2684ddaab485001ea
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-22 (Mon, 22 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

  Log Message:
  -----------
  [RISCV] Fix some errors in the vector part of the scheduler model for SiFive7.

-FP compare latency was too high.
-Compare instructions need to increase latency to assume no chaining
to later instructions.

vmv.x.s, vmv.s.x, vfmv.f.s, and vfmv.s.f aren't 8 cycles. From the
the perspective of the vector pipeline they are only 4 cycles. Though
vector to scalar has a much higher latency from the perspective
of the scalar pipeline. Will need to adjust in the future.

Reviewed By: michaelmaitland

Differential Revision: https://reviews.llvm.org/D151136