[all-commits] [llvm/llvm-project] c8eb53: [1/11][IR] Permit load/store/alloca for struct of ...

[Yueh-Ting (eop) Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c8eb535aed0368c20b25fe05bca563ab38dd91e9
      https://github.com/llvm/llvm-project/commit/c8eb535aed0368c20b25fe05bca563ab38dd91e9
  Author: eopXD <yueh.ting.chen at gmail.com>
  Date:   2023-05-19 (Fri, 19 May 2023)

  Changed paths:
    M llvm/docs/LangRef.rst
    M llvm/include/llvm/CodeGen/Analysis.h
    M llvm/include/llvm/IR/DataLayout.h
    M llvm/include/llvm/IR/DerivedTypes.h
    M llvm/include/llvm/IR/Type.h
    M llvm/lib/Analysis/ScalarEvolution.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/CodeGen/Analysis.cpp
    M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/IR/DataLayout.cpp
    M llvm/lib/IR/Type.cpp
    M llvm/lib/IR/Verifier.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
    M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
    M llvm/lib/Transforms/Scalar/SROA.cpp
    M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
    A llvm/test/Assembler/scalable-vector-struct.ll
    M llvm/test/CodeGen/AArch64/sme-aarch64-svcount.ll
    A llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
    A llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
    A llvm/test/Transforms/SROA/scalable-vector-struct.ll
    A llvm/test/Verifier/scalable-vector-struct-gep.ll

  Log Message:
  -----------
  [1/11][IR] Permit load/store/alloca for struct of the same scalable vector type

This patch-set aims to simplify the existing RVV segment load/store
intrinsics to use a type that represents a tuple of vectors instead.

To achieve this, first we need to relax the current limitation for an
aggregate type to be a target of load/store/alloca when the aggregate
type contains homogeneous scalable vector types. Then to adjust the
prolog of an LLVM function during lowering to clang. Finally we
re-define the RVV segment load/store intrinsics to use the tuple types.

The pull request under the RVV intrinsic specification is
riscv-non-isa/rvv-intrinsic-doc#198

---

This is the 1st patch of the patch-set. This patch is originated from
D98169.

This patch allows aggregate type (StructType) that contains homogeneous
scalable vector types to be a target of load/store/alloca. The RFC of
this patch was posted in LLVM Discourse.

https://discourse.llvm.org/t/rfc-ir-permit-load-store-alloca-for-struct-of-the-same-scalable-vector-type/69527

The main changes in this patch are:

Extend `StructLayout::StructSize` from `uint64_t` to `TypeSize` to
accommodate an expression of scalable size.

Allow `StructType:isSized` to also return true for homogeneous
scalable vector types.

Let `Type::isScalableTy` return true when `Type` is `StructType`
and contains scalable vectors

Extra description is added in the LLVM Language Reference Manual on the
relaxation of this patch.

Authored-by: Hsiangkai Wang <kai.wang at sifive.com>
Co-Authored-by: eop Chen <eop.chen at sifive.com>

Reviewed By: craig.topper, nikic

Differential Revision: https://reviews.llvm.org/D146872