[all-commits] [llvm/llvm-project] cb16b3: Revert "[X86] Remove patterns for ADC/SBB with imm...

[Hans via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cb16b33a03aff70b2499c3452f2f817f3f92d20d
      https://github.com/llvm/llvm-project/commit/cb16b33a03aff70b2499c3452f2f817f3f92d20d
  Author: Hans Wennborg <hans at chromium.org>
  Date:   2023-05-19 (Fri, 19 May 2023)

  Changed paths:
    M llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.cpp
    M llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimization.h
    M llvm/lib/Target/X86/X86CallFrameOptimization.cpp
    M llvm/lib/Target/X86/X86DynAllocaExpander.cpp
    M llvm/lib/Target/X86/X86FastISel.cpp
    M llvm/lib/Target/X86/X86FixupLEAs.cpp
    M llvm/lib/Target/X86/X86FrameLowering.cpp
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrAVX512.td
    M llvm/lib/Target/X86/X86InstrArithmetic.td
    M llvm/lib/Target/X86/X86InstrCompiler.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstructionSelector.cpp
    M llvm/lib/Target/X86/X86MCInstLower.cpp
    M llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
    M llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
    M llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
    M llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
    M llvm/test/CodeGen/X86/avxvnni-combine.ll
    M llvm/test/CodeGen/X86/cfi-xmm.ll
    M llvm/test/CodeGen/X86/extend-set-cc-uses-dbg.ll
    M llvm/test/CodeGen/X86/fast-regalloc-live-out-debug-values.mir
    M llvm/test/CodeGen/X86/leaFixup32.mir
    M llvm/test/CodeGen/X86/leaFixup64.mir
    M llvm/test/CodeGen/X86/limit-split-cost.mir
    M llvm/test/CodeGen/X86/machinesink-debug-inv-0.mir
    M llvm/test/CodeGen/X86/optimize-compare.mir
    M llvm/test/CodeGen/X86/peephole-fold-testrr.mir
    M llvm/test/CodeGen/X86/pr46827.ll
    M llvm/test/CodeGen/X86/push-cfi.ll
    M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
    M llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll
    M llvm/test/CodeGen/X86/switch-lower-peel-top-case.ll
    M llvm/test/CodeGen/X86/tail-call-conditional.mir
    M llvm/test/CodeGen/X86/tail-merge-after-mbp.mir
    M llvm/test/CodeGen/X86/throws-cfi-fp.ll
    M llvm/test/CodeGen/X86/twoaddr-dbg-value.mir
    M llvm/test/CodeGen/X86/update-terminator-debugloc.ll
    M llvm/test/CodeGen/X86/vecloadextract.ll
    M llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
    M llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
    M llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup-2.mir
    M llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir
    M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
    M llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir
    M llvm/test/DebugInfo/MIR/X86/live-debug-values-stack-clobber.mir
    M llvm/test/DebugInfo/MIR/X86/machinesink-subreg.mir
    M llvm/test/DebugInfo/MIR/X86/machinesink.mir
    M llvm/test/DebugInfo/MIR/X86/merge-inline-loc4.mir
    M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
    M llvm/test/DebugInfo/X86/debug-loc-asan.mir
    M llvm/test/DebugInfo/X86/debug-loc-offset.mir
    M llvm/test/DebugInfo/X86/location-range.mir
    M llvm/test/DebugInfo/X86/machinecse-wrongdebug-hoist.ll
    M llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
    M llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll
    M llvm/test/TableGen/x86-fold-tables.inc
    M llvm/test/Transforms/SampleProfile/pseudo-probe-twoaddr.ll
    M llvm/utils/TableGen/X86ManualFoldTables.def

  Log Message:
  -----------
  Revert "[X86] Remove patterns for ADC/SBB with immediate 8 and optimize during MC lowering, NFCI"

This caused compiler assertions, see comment on
https://reviews.llvm.org/D150107.

This also reverts the dependent follow-up change:

> [X86] Remove patterns for ADD/AND/OR/SUB/XOR/CMP with immediate 8 and optimize during MC lowering, NFCI
>
> This is follow-up of D150107.
>
> In addition, the function `X86::optimizeToFixedRegisterOrShortImmediateForm` can be
> shared with project bolt and eliminates the code in X86InstrRelaxTables.cpp.
>
> Differential Revision: https://reviews.llvm.org/D150949

This reverts commit 2ef8ae134828876ab3ebda4a81bb2df7b095d030 and
5586bc539acb26cb94e461438de01a5080513401.