[all-commits] [llvm/llvm-project] 2f7be4: [AArch64] Predicate for ROR immediate

[Evandro Menezes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f7be44622c4a3126cfd53f7d90ac22e1abf2c98
      https://github.com/llvm/llvm-project/commit/2f7be44622c4a3126cfd53f7d90ac22e1abf2c98
  Author: Evandro Menezes <evandro+llvm at gcc.gnu.org>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
    M llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
    M llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
    M llvm/lib/Target/AArch64/AArch64SchedPredicates.td

  Log Message:
  -----------
  [AArch64] Predicate for ROR immediate

Add a common predicate for when the `ROR` immediate or "Bitfield
extract, one register" idiom is used for `EXTR` or "Bitfield extract,
two registers".

Differential revision: https://reviews.llvm.org/D150832