[all-commits] [llvm/llvm-project] 3f43ab: [RISCV] Reduce dependency on RISCV::RVVBitsPerBloc...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f43abc9e78cce99741f7c8cf54552c95cc98d9f
      https://github.com/llvm/llvm-project/commit/3f43abc9e78cce99741f7c8cf54552c95cc98d9f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M clang/lib/AST/ASTContext.cpp
    M clang/lib/Sema/SemaType.cpp

  Log Message:
  -----------
  [RISCV] Reduce dependency on RISCV::RVVBitsPerBlock for calculating vector size for -mrvv-vector-bits.

We can use the minimum value of the BuiltinType's ElementCount and
the element size.

This needs to be done to support LMUL!=1 types anyway.

I did have to make an ordering change in the error checks in
HandleRISCVRVVVectorBitsTypeAttr to check if the type is an RVV
VLS type before checking the size.