[all-commits] [llvm/llvm-project] fa0a39: [RISCV] Fix assertion when casting LMUL!=1 RVV typ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fa0a39113a28448529f62d3ea30a7b7a8066f231
      https://github.com/llvm/llvm-project/commit/fa0a39113a28448529f62d3ea30a7b7a8066f231
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-18 (Thu, 18 May 2023)

  Changed paths:
    M clang/lib/AST/ASTContext.cpp
    M clang/test/Sema/attr-riscv-rvv-vector-bits.c

  Log Message:
  -----------
  [RISCV] Fix assertion when casting LMUL!=1 RVV types to GNU types with -mrvv-vector-bits.

We need to call isRVVVLSBuiltinType() before calling getRVVTypeSize().