[all-commits] [llvm/llvm-project] 77589e: [X86] Remove patterns for shift/rotate with immedi...

[KanRobert via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 77589e945f0d167bd46ed3218b81c16af1e917ae
      https://github.com/llvm/llvm-project/commit/77589e945f0d167bd46ed3218b81c16af1e917ae
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2023-05-17 (Wed, 17 May 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrShiftRotate.td
    M llvm/lib/Target/X86/X86MCInstLower.cpp
    M llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
    M llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
    M llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir
    M llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir
    M llvm/test/CodeGen/X86/fast-isel-shift.ll
    M llvm/test/CodeGen/X86/gpr-to-mask.ll
    M llvm/test/CodeGen/X86/is_fpclass.ll

  Log Message:
  -----------
  [X86] Remove patterns for shift/rotate with immediate 1 and optimize during MC lowering

It's first suggested by @craig.topper  in D150068. I think there are at least three pros

1. This can reduce the patterns during ISEL, as a result, reducing the bytes in X86GenDAGISel.inc
2. The patterns for shift/rotate with immediate 1 look quite similar to shift/rotate with immediate 8. So this can be seen as eliminating "duplicate" code.
3. Delay the optimization from imm8 to imm1, so that the previous optimization passes do not need to handle the version of imm1

It improves fast isel code and makes X86DomainReassignment work for shifts by 1, but regressed global isel, though no one should care.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D150107