[all-commits] [llvm/llvm-project] 198f6a: [AArch64] Combine add(extract v1i64) into v1i64 add

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 198f6a9f36e4ffd056e27fac8c0636476958d3cf
      https://github.com/llvm/llvm-project/commit/198f6a9f36e4ffd056e27fac8c0636476958d3cf
  Author: David Green <david.green at arm.com>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/add-extract.ll
    M llvm/test/CodeGen/AArch64/arm64-vshift.ll

  Log Message:
  -----------
  [AArch64] Combine add(extract v1i64) into v1i64 add

This helps fix a regression from D148309 where a shift + add was no longer
combined into a ssra. It looks for add's with v1i64 extract operands and
converts them to v1i64 adds. The other operand needs to be something that is
easily converted to a v1i64, in this case it currently just checks for a load.

Some of the code in performAddSubCombine has been cleaned up whilst I was here.

Differential Revision: https://reviews.llvm.org/D148311