[all-commits] [llvm/llvm-project] 8f43c3: [RISCV] Rework how implied SP operands work in the...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8f43c3f49ecea404458a2fbde126e20c6d404a14
      https://github.com/llvm/llvm-project/commit/8f43c3f49ecea404458a2fbde126e20c6d404a14
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

  Log Message:
  -----------
  [RISCV] Rework how implied SP operands work in the disassembler. NFC

Previously we added the SP operands when an immediate operand was added
to certain opcodes.

This patch moves it to a post processing step using the information
in MCInstrDesc. This avoids an explicit opcode list in RISCVDisassembler.cpp.

In considered using a custom DecoderMethod, but the bit swizzling we
need to do for the immediates on these instructions made that
unattractive.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D149931