[all-commits] [llvm/llvm-project] 8cf5f7: [RISCV] Avoid RegScavenger::forward in RISCVMakeCo...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8cf5f730fb02d7bd794ca68764b7eaf0cb329a6c
      https://github.com/llvm/llvm-project/commit/8cf5f730fb02d7bd794ca68764b7eaf0cb329a6c
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp

  Log Message:
  -----------
  [RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt

RegScavenger::backward is preferred because it does not rely on accurate
kill flags.

Differential Revision: https://reviews.llvm.org/D150562


  Commit: af0121fb8f793e5142d445cc2192e5c4a33bb21f
      https://github.com/llvm/llvm-project/commit/af0121fb8f793e5142d445cc2192e5c4a33bb21f
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/agpr-copy-sgpr-no-vgprs.mir
    M llvm/test/CodeGen/AMDGPU/copy-vgpr-clobber-spill-vgpr.mir

  Log Message:
  -----------
  [AMDGPU] Add implicit uses to AGPR copy MIR tests

Some tests were using liveins or IMPLICIT_DEFs to add fake live
registers, but that only works if you track liveness forwards. Add some
implicit uses too, so that it also works if you track liveness
backwards.

Some of these tests were using the regmask amdgpu_allvgprs but that is a
clobber not a use.

Differential Revision: https://reviews.llvm.org/D150570


Compare: https://github.com/llvm/llvm-project/compare/64599ac97eb1...af0121fb8f79