[all-commits] [llvm/llvm-project] 9a24ba: Correct the sort logic in AsmMatcherEmmitter.cpp

[XinWang10 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9a24ba2397ea72c5124dbc75b4dd9ee9db676518
      https://github.com/llvm/llvm-project/commit/9a24ba2397ea72c5124dbc75b4dd9ee9db676518
  Author: Wang, Xin10 <xin10.wang at intel.com>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86InstrArithmetic.td
    M llvm/lib/Target/X86/X86InstrControl.td
    M llvm/test/MC/Disassembler/X86/x86-64.txt
    M llvm/test/MC/X86/I86-64.s
    M llvm/test/MC/X86/pr22028.s
    M llvm/test/MC/X86/x86-16.s
    M llvm/test/MC/X86/x86_64-encoding.s
    M llvm/utils/TableGen/AsmMatcherEmitter.cpp

  Log Message:
  -----------
  Correct the sort logic in AsmMatcherEmmitter.cpp

The logic from line 633 to 640 is specific for ARM as the comments said, it will make all the targets will prefer to using instruction with more predicates when compiler do AsmMatching.
And for code from line 642 to 649, X86 want to use the order records written in source file to sort the instructions. So X86 could be affected by this logic. (These code could be arrived only by X86)
After change this, seems AVX instructions have not be affected but it exposed some other errors for instruction push and call.
CALLpcrel16 could not be used in 64 bit mode, we need add Predicate for it. And for push instruction, previously because pushi32 has predicates = [Not64bitmode], so it precede pushi16, which is incorrect here, we should get pushw here and it also align with gcc.

Reviewed By: skan

Differential Revision: https://reviews.llvm.org/D150436