[all-commits] [llvm/llvm-project] fbe1c0: [LLVM][Uniformity] Improve detection of uniform re...

[Sameer Sahasrabuddhe via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fbe1c0616fa83d39ebad29cfefa020bbebd90057
      https://github.com/llvm/llvm-project/commit/fbe1c0616fa83d39ebad29cfefa020bbebd90057
  Author: Sameer Sahasrabuddhe <sameer.sahasrabuddhe at amd.com>
  Date:   2023-05-16 (Tue, 16 May 2023)

  Changed paths:
    M llvm/include/llvm/ADT/GenericUniformityImpl.h
    M llvm/include/llvm/CodeGen/RegisterBankInfo.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/Analysis/UniformityAnalysis.cpp
    M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/atomics.mir
    R llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge.mir
    A llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-loop-diverge.mir
    R llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/irreducible/irreducible-1.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/never-uniform.mir
    R llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-diverge-gmir.mir
    A llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/temporal-divergence.mir
    A llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/hidden-diverge.mir
    A llvm/test/Analysis/UniformityAnalysis/AMDGPU/deprecated/irreducible-1.mir
    M llvm/test/Analysis/UniformityAnalysis/AMDGPU/temporal_diverge.ll

  Log Message:
  -----------
  [LLVM][Uniformity] Improve detection of uniform registers

The MachineUA now queries the target to determine if a given register holds a
uniform value. This is determined using the corresponding register bank if
available, or by a combination of the register class and value type. This
assumes that the target is optimizing for performance by choosing registers, and
the target is responsible for any mismatch with the inferred uniformity.

For example, on AMDGPU, an SGPR is now treated as uniform, except if the
register bank is VCC (i.e., the register holds a wave-wide vector of 1-bit
values) or equivalently if it has a value type of s1.

 - This does not always work with inline asm, where the register bank or the
   value type might not be present. We assume that the SGPR is uniform, because
   it is not expected to be s1 in the vast majority of cases.
 - The pseudo branch instruction SI_LOOP is now hard-coded to be always
   divergent, although its condition is an SGPR.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D150438