[all-commits] [llvm/llvm-project] 6e6bed: [RISCV] Add test cases for forming vfwmacc when wi...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6e6bed575777be7be55482090414e153ed6f7557
      https://github.com/llvm/llvm-project/commit/6e6bed575777be7be55482090414e153ed6f7557
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-14 (Sun, 14 May 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfwmacc.ll

  Log Message:
  -----------
  [RISCV] Add test cases for forming vfwmacc when widening from f16 to f64. NFC


  Commit: f2a05c64e3880278c8b3afa5a78a93eb26d244e5
      https://github.com/llvm/llvm-project/commit/f2a05c64e3880278c8b3afa5a78a93eb26d244e5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-05-14 (Sun, 14 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Add RISCVISD nodes for VWFMADD_VL.

Use it to replace isel patterns with a DAG combine of FP_EXTEND_VL+VFMADD_VL.

This makes it similar to how other widening operations are handled.

I plan to use this to make it easier to form tail undisturbed vfwmacc.


Compare: https://github.com/llvm/llvm-project/compare/48bc71505e03...f2a05c64e388