[all-commits] [llvm/llvm-project] 0bc739: [GlobalISel] Handle ptr size != index size in IRTr...

[Krzysztof Drewniak via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0bc739a4ae84f44d9bb0b3b8f9505772449859a9
      https://github.com/llvm/llvm-project/commit/0bc739a4ae84f44d9bb0b3b8f9505772449859a9
  Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
  Date:   2023-05-12 (Fri, 12 May 2023)

  Changed paths:
    M llvm/lib/CodeGen/CodeGenPrepare.cpp
    M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces.ll

  Log Message:
  -----------
  [GlobalISel] Handle ptr size != index size in IRTranslator, CodeGenPrepare

While the original motivation for this patch (address space 7 on
AMDGPU) has been reworked and is not presently planned to reach IR
translation, the incorrect (by the spec) handling of index offset
width in IR translation and CodeGenPrepare is likely to trip someone
- possibly future AMD, since we have a p7:160:256:256:32 now, so we
convert to the other API now.

Reviewed By: aemerson, arsenm

Differential Revision: https://reviews.llvm.org/D143526