[all-commits] [llvm/llvm-project] 1a8558: [RISCV] Add support for V extenstion in SiFive7

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1a855819a87f426bdbd83c815fa47ca01fdf928f
      https://github.com/llvm/llvm-project/commit/1a855819a87f426bdbd83c815fa47ca01fdf928f
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-05-10 (Wed, 10 May 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td

  Log Message:
  -----------
  [RISCV] Add support for V extenstion in SiFive7

Add scheduling information for vector extension in SiFive7,
while using new LMUL & SEW scheduling constructs.

Differential Revision: https://reviews.llvm.org/D149495